Transistor package

专利摘要:
The present invention relates to a transistor package, comprising: a die pad; A heat sink integral with one surface of the die pad and formed with a circular fastening groove, the heat sink having a long groove crossing the fastening groove; A transistor chip bonded to an upper surface of the die pad; A lead spaced apart from and disposed on the other surface of the die pad and electrically connected to the transistor chip; And a package body in which the die pad, the heat sink, the transistor chip, and the lead electrically connected to the lead body are embedded and encapsulated by a molding resin, and the molding resin is filled in the long groove of the heat sink. By increasing the bonding force between the package body and the heat sink so that the interface generated by the molding process does not proceed to the package crack by the reliability test, the thickness of the lead, the die pad and the heat sink is the same, thereby making the transistor according to the prior art possible. Compared to the package, the interface generation rate can be remarkably improved.
公开号:KR19980044546A
申请号:KR1019960062639
申请日:1996-12-06
公开日:1998-09-05
发明作者:전기영
申请人:김광호；삼성전자 주식회사；
IPC主号:

专利说明:

Transistor package
The present invention relates to a transistor package. More particularly, the present invention relates to a transistor package in which a molding resin is filled in a long groove crossing a fastening groove of a heat sink to improve a bonding force between the heat sink and the package body.
In recent years, electronic products are rapidly progressing in light weight, small size, and mass storage for convenience of portability and installation, and the corresponding technologies include ONE CHIP, which manufactures several components into one component, and multiple components into one component. It is being developed in the direction of miniaturization and large capacity of modularization and mounting components mounted on a package. An example of the above technology is a smart power chip and a smart power transistor package.
Here, a smart power integrated circuit (smart power IC) refers to a technology for integrating a power transistor and an integrated circuit for controlling the same into one chip, and the smart power transistor package includes the power transistor and the control chip in one package. Means technology to be implemented. After the two semiconductor chips are packaged, the smart power integrated circuit and the smart power transistor package may be products having the same characteristics although the internal structure of the package is different.
As the same example, there are a wafer scale integrated circuit (wafer scale IC) in which several chips are integrated on one wafer, and a multichip module mounting several chips in one package.
Since the above-mentioned techniques have many problems in electrical and heat dissipation design, manufacturing process, inspection, yield and reliability, each solution to this problem is essential to commercialize the technique.
1 is a plan view showing a lead frame for a transistor applied to the prior art.
FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1.
1 and 2, a transistor lead frame 100 includes a die pad 20 on which a transistor chip is mounted; It is integrally formed on the upper surface of the die pad 20, and has a structure that can quickly dissipate heat generated when power is applied to the transistor chip to be mounted on the die pad 20 to the atmosphere A heat sink 30 having a fastening groove 32 formed at a center portion thereof; A plurality of leads 40 formed integrally with the bottom surface of the die pad 20 and spaced apart from each other; And a dam bar 60 having the same thickness as that of the lead between the leads 40, and more specifically, formed at the outermost side of the lid, which is encapsulated by a molding process to be prevented from overflowing the molding resin. It is a structure to include.
Here, referring to FIG. 2, a vertical structure of the lead frame 100 will be described. In the lead frame 100, the die pad 20 and the heat sink 30 have the same thickness and are at least 3 with respect to the lead 40. It has a thickness of ˜4 times, and has a structure which is down-set several times rather than the lead 40.
3 is a plan view illustrating a transistor package using the lead frame of FIG. 1.
4 is a rear view of FIG. 3.
3 and 4, the transistor package 200 according to the related art has a structure in which an upper end and a rear surface of the heat sink 30 and a lead 40 protrude from the package body 50.
Here, the package body 50 will be described in more detail. The package body 50 may include a die pad 20 and a die pad 20 of the lead frame 100 mentioned in the description of FIGS. 1 and 2. The top surface of the transistor chip (not shown) electrically bonded by solder and the tip portion of the lead 40 electrically connected to the transistor chip are embedded and encapsulated by an epoxy-based molding resin.
And, in more detail with respect to the heat dissipation plate 30, the heat dissipation plate 30 is a state in which a fastening groove 32 formed in the upper center portion is filled with a molding resin in a predetermined portion, the rear surface of the package body The reason for the exposure to 50 is to rapidly dissipate high heat generated when power is applied, for example, heat higher than room temperature, to the air in the power transistor.
However, the transistor package 200 having such a structure has a different thermal expansion coefficient between the epoxy resin constituting the package body 50 and the heat sink 30 and the lead 40 in the molding process. And interfacial peeling occurs between the lid 40 and the package body 50. In addition, since the thickness of the heat sink 20 is relatively thicker than the thickness of the lead 40, the amount of thermal expansion is greater even with the same coefficient of thermal expansion. Will occur intensively.
Here, although the interface peeling does not directly cause a defect of the transistor package 200, the amount of water supplied into the package body 50 is increased by a reliability test performed in a high temperature and high humidity atmosphere. As the amount of water increases in volume due to high heat, an increase in interfacial peeling proceeds innovatively, resulting in a package crack in which the package body 50 is minutely broken.
This package crack reduces the mechanical strength of the package, and causes the displacement of the semiconductor chip and the bonding wire encapsulated inside the package body 50, thereby acting as a factor to lower the electrical characteristics.
Accordingly, an object of the present invention is to provide a transistor package that can improve the mechanical and electrical reliability of a transistor package by increasing the bonding force between the heat sink and the package body to prevent the progress of interfacial peeling.
1 is a plan view showing a lead frame for a transistor applied to the prior art.
FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1. FIG.
3 is a plan view illustrating a transistor package using the lead frame of FIG. 1.
4 is a rear view of FIG. 3.
5 is a plan view showing a lead frame for a transistor to which the present invention is applied.
6 is a cross-sectional view taken along the line VI-VI of FIG. 5.
FIG. 7 is a plan view illustrating a transistor package using the lead frame of FIG. 5. FIG.
8 is a rear view of FIG. 7.
※ Description of main part of drawing ※
120: die pad 130: heat sink
132: heat sink fastening groove 134: groove (groove)
140: lead 150: package body
160: dam bar 200: lead frame
400: transistor package
In order to achieve the above object, the present invention provides a die pad; A heat sink integral with one surface of the die pad and formed with a circular fastening groove, the heat sink having a long groove crossing the fastening groove; A transistor chip bonded to an upper surface of the die pad; A lead spaced apart from and disposed on the other surface of the die pad and electrically connected to the transistor chip; And a package body in which the die pad, the heat sink, the transistor chip, and the lead electrically connected to the lead body are embedded and encapsulated by a molding resin, and the molding resin is filled in the long groove of the heat sink. do.
Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
5 is a plan view illustrating a lead frame for a transistor to which the present invention is applied.
FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5.
5 and 6, the lead frame 300 applied to the present invention includes a die pad 120 on which a transistor chip is mounted; It is integrally formed on the upper surface of the die pad 120, and has a structure that can quickly dissipate heat generated when power is applied to the transistor chip to be mounted on the die pad 120 to the atmosphere A heat sink 130 formed with a long groove 134 crossing the fastening groove 132 in the center portion; A plurality of leads 140 formed integrally with the bottom surface of the die pad 120 and spaced apart from each other; And a dam bar 160 having the same thickness as the lead between the leads 140 and formed in the outermost part encapsulated by a molding process which will be performed later, to prevent the overflow of the molding resin. It is a structure to include.
Since the lead frame 300 applied to the present invention has a thickness of the die pad 120 and the heat sink 130 with respect to the thickness of the lead 140 unlike the conventional lead frame 100, the package body ( It is less likely that interface peeling with 150 occurs.
FIG. 7 is a plan view illustrating a transistor package using the lead frame of FIG. 5.
8 is a rear view of FIG. 7.
7 and 8, the transistor package 400 according to the present invention has a structure in which an upper end and a rear surface of the heat sink 130 and a lead 140 protrude from the package body 150.
Here, the package body 150 will be described in more detail. The package body 150 includes the die pad 120 and the die pad 120 of the lead frame 300 mentioned in the description of FIGS. 5 and 6. The top surface of the transistor chip (not shown) electrically bonded by solder and the tip portion of the lead 140 electrically connected to the transistor chip are embedded and encapsulated by an epoxy-based molding resin.
And, in more detail with respect to the heat sink 130 is a feature of the present invention, the heat sink 130 is a long groove 134 formed across the fastening groove 132 and the fastening groove 132 formed in the upper center portion. ) Is a state in which a molding resin is filled inside, and the rear surface thereof is exposed to the package body 150 due to the high temperature generated when the power is applied, for example, a heat higher than room temperature in the air. This is to dissipate heat quickly.
In the transistor package 400 having the above structure, the molding resin is filled in the long groove 134 formed across the fastening groove 132 of the heat sink 130 by the difference in the coefficient of thermal expansion between the heat sink 130 and the molding resin. To increase the coupling force between the package body 150 and the heat sink 130.
In addition, in the thermal expansion of the heat dissipation plate 130, the long groove 134 serves to offset the amount of thermal expansion to a minimum because the opposite directions of expansion of each of the two sides face each other. Since the direction of the long groove 134 is formed to be the same as the width direction of the heat sink 130, it is suppressed that the heat sink 130 is thermally expanded in a direction perpendicular to the forming direction of the long groove 134. As a result, the moldability of the molding resin filled in the long groove 134 is improved to increase the bonding force between the package body 150 and the heat sink 130.
Although the present invention has been described with reference to the above-described embodiments, it should be understood that various modifications and embodiments of the present invention may be implemented by those skilled in the art without being limited thereto. It is self-made.
According to the structure of the present invention, there is an effect that the reliability of the package can be improved by increasing the bonding force between the package body and the heat sink so that the interface peeling caused by the molding process does not proceed to the package crack by the reliability test. In addition, the present invention also has the additional effect of remarkably improving the interface peeling generation rate compared to the transistor package according to the prior art by making the thicknesses of the leads, the die pads, and the heat sinks the same.

权利要求:
Claims (3)
[1" claim-type="Currently amended] Die pads;
A heat sink integral with one surface of the die pad and formed with a circular fastening groove, the heat sink having a long groove crossing the fastening groove;
A transistor chip bonded to an upper surface of the die pad;
A lead spaced apart from and disposed on the other surface of the die pad and electrically connected to the transistor chip;
A package body in which an electrically connected front end portion of the die pad, the heat sink, the transistor chip, and the lead are embedded and sealed by a molding resin;
And a molding resin filled in the long grooves of the heat sink.
[2" claim-type="Currently amended] The transistor package of claim 1, wherein the long groove has the heat sink formed along a width direction of the heat sink.
[3" claim-type="Currently amended] The transistor package of claim 1, wherein thicknesses of the lead, the die pad, and the heat sink are all the same.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1996-12-06|Application filed by 김광호, 삼성전자 주식회사

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1996-12-06|Priority to KR1019960062639A

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1998-09-05|Publication of KR19980044546A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019960062639A|KR19980044546A|1996-12-06|1996-12-06|Transistor package|